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19-4605; Rev 0; 6/09
16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
General Description
The MAXQ8913 is a single-chip servo controller designed as a complete solution for dual axis optical image stabilization (OIS) applications. The device incorporates all the necessary elements for conditioning of sensor signals, analog-to-digital conversion, digital servo algorithm implementation using a 16-bit RISC microcontroller, and digital-to-analog conversion, as well as including dual servo amplifiers. Even though the device is targeted for OIS applications, it can be effectively used in many other types of servo control. The MAXQ8913 supports both voice coil and stepper motor applications. The MAXQ8913 includes four op amps; a 7-channel, 12-bit ADC; dual 10-bit differential DACs; and dual 8-bit single-ended DACs. It also contains 64KB of flash memory, 4KB of RAM, 4KB of ROM, a 16-bit timer/counter, a universal asynchronous/synchronous receiver-transmitter (USART), an I2C port, and an SPITM master/slave port. For the ultimate in low-power performance, the OIS device includes a low-power sleep mode, the ability to selectively disable peripherals, and multiple power-saving operating modes.
Features
High-Performance, Low-Power, 16-Bit MAXQ(R) RISC Core One-Cycle, 16 x 16 Hardware Multiply/Accumulate with 48-Bit Accumulator Two Current Sinks for Driving Hall-Effect Elements Four DACs DC to 10MHz Operation; Approaching 1MIPS per MHz 2.7V to 3.6V Logic/Analog Operating Voltage 33 Instructions, Most Single Cycle Three Independent Data Pointers Accelerate Data Movement with Automatic Increment/Decrement 16-Level Hardware Stack 16-Bit Instruction Word, 16-Bit Data Bus 16 x 16-Bit General-Purpose Working Registers Optimized for C Compilers Memory Features 64KB Flash Memory 4KB of Internal Data RAM 4KB of Utility ROM JTAG Bootloader for Programming and Debug Peripherals Four Operational Amplifiers 12-Bit SAR ADC with Internal Reference and Autoscan Up to 312ksps Sample Rate Seven-Input Mux (Four Internally Connected to Op-Amp Outputs, One Internally Connected to Temp Sensor, and Two Connected to Uncommitted External Pins) Brownout Reset Generation 16-Bit Programmable Timer/Counter USART, I2C, and SPI Master/Slave On-Chip Power-On Reset/Brownout Reset Programmable Watchdog Low-Power Consumption 3mA (max) at 10MHz Flash Operation at 3.3V 4.5A (max) in Stop Mode Low-Power Power-Management Mode (PMM)
MAXQ8913
Applications
Digital Camera and Cell Phone Optical Image Stabilization Servo Loop Control Tone Generation with Speaker Drive
Ordering Information
PART MAXQ8913EWG+T TEMP RANGE -40C to +85C PIN-PACKAGE 58 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel.
Pin Configuration appears at end of data sheet.
SPI is a trademark of Motorola, Inc. MAXQ is a registered trademark of Maxim Integrated Products, Inc.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
ABSOLUTE MAXIMUM RATINGS
Voltage Range on All Pins (including AVDD, DVDD) Relative to Ground .................................-0.5V to +3.6V Voltage Range on Any Pin Relative to Ground except AVDD, DVDD...........................-0.5V to (VDVDD + 0.5V) Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(VDVDD = VAVDD = 2.7V to 3.6V, TA = -40C to +85C.) (Note 1)
PARAMETER Digital Supply Voltage Digital Operating Voltage Regulator Voltage Output Analog Supply Voltage Ground Digital Power-Fail Reset Voltage Active Current (Note 3) VREG18 VAVDD GND VRST IDD_HFX3 IDD_HFX4 I STOP_1 Stop-Mode Current I STOP_2 I STOP_3 Stop-Mode Resume Time Input Low Voltage on HFXIN Input Low Voltage on All Other Port Pins Input High Voltage on HFXIN Input High Voltage on All Other Port Pins Input Hysteresis (Schmitt) Output Low Voltage for All Port Pins Except SHDNL, SHDNR Output Low Voltage for SHDNL, SHDNR Output High Voltage for All Port Pins I/O Pin Capacitance t STOP_1 t STOP_2 VIL1 VIL2 VIH1 VIH2 VIHYS VOL VOL VOH CIO I OL = 4mA (Note 8) I OL = 1.5mA I OH = -4mA (Note 8) Guaranteed by design VDGND VDGND VDVDD - 0.4 15 (Note 2) VAVDD = VDVDD AGND = DGND Monitors VDVDD fCK = 10MHz, VDVDD = 2.7V fCK = 10MHz, VDVDD = 3.3V (Notes 4, 5) (Notes 4, 6) (Notes 4, 7) Internal regulator on Internal regulator off, brownout or SVM on VDGND VDGND 0.75 x VDVDD 0.70 x VDVDD 0.18 0.4 0.4 15 375 0.20 x VDVDD 0.30 x VDVDD VDVDD VDVDD 0.2 SYMBOL VDVDD CONDITIONS VAVDD = VDVDD MIN VRST VRST 1.71 2.7 0 2.58 0 1.8 TYP 3.3 MAX 3.6 3.6 1.89 3.6 0 2.68 2.2 3.0 4.5 40 500 s V V V V V V V V pF A UNITS V V V V V V mA
2
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16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDVDD = VAVDD = 2.7V to 3.6V, TA = -40C to +85C.) (Note 1)
PARAMETER Input Low Current for Port Pins Input-Leakage Current Input Pullup Resistor CLOCK SOURCE External Clock Frequency External Clock Duty Cycle Internal Ring Oscillator System Clock Frequency FLASH AC CHARACTERISTICS System Clock During Flash Programming/Erase Program Time Page Erase Time Mass Erase Time Write/Erase Cycles Data Retention ANALOG-TO-DIGITAL CONVERTER (Note 9) ADC Clock Frequency Input Voltage Range Analog Input Capacitance f SCLK VAIN CAIN IAVDD1 Current Consumption IAVDD2 IASTOP Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Gain Temperature Coefficient Signal-to-Noise Plus Distortion Spurious-Free Dynamic Range Throughput ADC Setup Time Input-Leakage Current SINAD SFDR f IN = 1kHz f IN = 1kHz 16f SCLK samples tADC_SETUP (Note 11) I ILA Shutdown or conversion stopped; AIN0/AIN1 and VAEREF 69 76 312 4 1 0.5 INL DNL No missing codes from +25C to +85C f SCLK = 5MHz, internal reference f SCLK = 5MHz, external reference (internal reference disabled) Power-down mode 12 1 2 1 10 1 Unipolar (single-ended) Bipolar (differential) (Note 10) 0.1 0 -VREF/2 16 3.0 800 2.5 Bits LSB LSB LSB % ppm/C dB dB ksps s A 5 VREF +VREF/2 MHz V pF mA A TA = +25C t PROG t ERASETME 2 20 20 20 1000 100 40 40 40 MHz s ms ms Cycles Years fCK DC fHFIN t XCLK_DUTY DC 40 1 10 10 60 MHz % MHz MHz SYMBOL IIL IL RPU VIN = 0.4V Internal pullup disabled -300 30 70 CONDITIONS MIN TYP MAX 100 +300 110 UNITS A nA k
MAXQ8913
ANALOG-TO-DIGITAL CONVERTER PERFORMANCE (VREF = 3V, 0.1F capacitor on REFA, fSCLK = 5MHz)
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16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDVDD = VAVDD = 2.7V to 3.6V, TA = -40C to +85C.) (Note 1)
PARAMETER Autoscan Throughput SYMBOL CONDITIONS All channels active MIN TYP MAX 39 UNITS ksps per channel V s V ppm/C
ANALOG-TO-DIGITAL CONVERTER REFERENCE Internal Reference Voltage Internal Reference Voltage Startup Time External Reference Voltage Input Internal Reference Voltage Drift Reference Settle Time (Switching ADC Reference from Either Internal or External Reference to AVDD) Reference Output SUPPLY VOLTAGE MONITOR Supply Voltage Set Point Supply Voltage Increment Resolution Supply Voltage Default Set Point Supply Voltage Monitor Start Time t SVMST t SVM_SU1 t SVM_SU2 Changing from one set point to another set point Exit from stop mode SVTR 2.7 80 100 2.7 50 2 s 8 3.5 120 V mV V s VAIREF tAIREF VAEREF VADRIFT tAAVDD_
SETUP
1.44
1.5
1.56 50
0.9 Guaranteed by design
VAVDD + 0.05 50
(Note 12)
4
Samples
VREFA
VREF
V
Supply Voltage Monitor Setup Time
CLASS D AMPLIFIER CONTROL DACs, 10-BIT DACs Resolution Full-Scale Output Voltage Output Common-Mode Voltage DC Output Impedance Integral Nonlinearity Differential Nonlinearity Settling Time Digital Feedthrough Glitch Impulse Update Rate Major carry transition (Note 13) 100 VFS VCM ZOUT INL DNL Guaranteed monotonic by design From 1/4 FS to 3/4 FS to 1 LSB -1 At DC, per side Code 0 = -2.5, code 1023 = +2.5, VREF = 1.5V 10 2.3 1.15 2.5 1.25 10 2 0.10 2 0.15 12 2.8 1.4 Bits V V k LSB LSB s nV-s nV-s ksps
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16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDVDD = VAVDD = 2.7V to 3.6V, TA = -40C to +85C.) (Note 1)
PARAMETER Resolution Full-Scale Output Voltage Output Common-Mode Voltage DC Drive Capability Integral Nonlinearity Differential Nonlinearity Settling Time Update Rate OP AMP A, B, C, D Offset Voltage Offset Drift Input Bias Current Common-Mode Rejection Ratio Gain Bandwidth Product Input Common-Mode Range TEMPERATURE SENSOR Sensitivity Raw Accuracy CURRENT SINK Resolution Full-Scale Sink Current Zero-Scale Sink Current LSB Size SPI Master Operating Frequency SCLK Output Pulse WidthHigh/Low I/O Rise/Fall Time (This parameter is device dependent.) MOSI Output Valid to SCLK Sample Edge (MOSI Setup) MOSI Output Hold After SCLK Sample Edge IS15 IS0 LSB 1/tMCK tMCH, tMCL tMCK/ 2 - tRF CL = 15pF, pullup = 560 tMCK/ 2 - tRF tMCK/ 2 - tRF 16 Code 0 = 0, code 1 = 62.5A, code 255 = 15.94mA Code = 255, VDS = 2V, VREF = 1.5V Code = 0, VDS = 2V VDS = 2V, VREF = 1.5V 8 14.9 15.94 0 62.5 f SYS/2 18.0 1 Bits mA A A MHz ns Code 0 = -273.15C; absolute 0; 8 LSB/C for VREF = 1.5V, 12-bit ADC; 4 LSB/C for VREF = 3.0V No correction, T = 300K (Note 14) -6 2.9304 +6 mV/C C VOS VOSDRIFT IBIAS CMMR GB CMRNG 1 VCM = 2V VCM = 2V TA = +25C (Note 13) 60 80 > 200 VAVDD -8 2 10 1 +8 mV V/C nA dB kHz V VFS VCM IDRIVE INL DNL Guaranteed monotonic by design From 1/4 FS to 3/4 FS to 1 LSB (Note 14) 100 -1 Code 0 = 0.35, code 255 = 2.35, VREF = 1.5 Code = 128, VREF = 1.5V (Note 14) SYMBOL CONDITIONS MIN 8 0.30 to 2.20 1.25 1 1 0.5 5 0.35 to 2.35 1.35 0.45 to 2.7 1.55 TYP MAX UNITS Bits V V mA LSB LSB s ksps
MAXQ8913
DAC3 AND DAC4 INCLUDING BUFFER
SPI: MASTER MODE (See Figures 1, 2)
tRF
ns
tMOV tMOH
ns ns
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16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDVDD = VAVDD = 2.7V to 3.6V, TA = -40C to +85C.) (Note 1)
PARAMETER SCLK Last Sample Edge to MOSI Output Change (MOSI Last Hold) MISO Input Valid to SCLK Sample Edge (MISO Setup) MISO Input Hold After SCLK Sample Edge SPI Slave Operating Frequency SCLK Input Pulse-Width High/Low I/O Rise/Fall Time (This parameter is device dependent.) SSEL Active to First Shift Edge MOSI Input to SCLK Sample Edge Rise/Fall Setup MOSI Input from SCLK Sample Edge Transition Hold MISO Output Valid After SCLK Shift Edge Transition SSEL Inactive to Next SSEL Asserted SCLK Inactive to SSEL Deasserted MISO Output Disabled After SSEL Edge Deasserted SYMBOL tMLH tMIS tMIH (Note 13) CONDITIONS MIN tMCK/ 2 - tRF 2tRF 0 TYP MAX UNITS ns ns ns
SPI: SLAVE MODE (See Figures 1, 3) 1/t SCK t SCH, t SCL t SCK/ 2 - tRF CL = 15pF, pullup = 560 tRF tRF tRF (Note 13) t SYS + tRF tRF 2t SYS + 2tRF 2tRF 16 f SYS/4 kHz ns
tRF t SSE t SIS t SIH t SOV t SSH t SD t SLH
ns ns ns ns ns ns ns ns
Note 1: Note 2: Note 3:
Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: 6
Specifications to -20C are guaranteed by design and are not production tested. Connect to ground through a 1F capacitor. Crystal connected to HFXIN, HFXOUT. Operating in /1 mode. Measured on the DVDD pin and the device not in reset. All inputs are connected to GND or DVDD. Outputs do not source/sink any current. One timer B enabled, with the device executing code from flash. ISTOP is the total current into the device when the device is in stop mode. Regulator, brownout disabled. Stop mode current through AVDD and DVDD. Regulator disabled, brownout enabled. Stop mode current through AVDD and DVDD. Regulator enabled, brownout enabled. IOH(MAX) + IOL(MAX) for all outputs combined should not exceed 35mA to meet the specification. VREF = VAVDD. The operational input voltage range for each individual input of a differentially configured pair is from GND to AVDD. The operational input voltage difference is from -VREF/2 to +VREF/2. The typical value is applied when a conversion is requested with ADPMO = 0. Under these conditions, the minimum delay is met. If ADPMO = 1, the user is responsible for ensuring the 4s delay time is met. Total on-board decoupling capacitance on the AVDD pin < 100nF. The output impedance of the regulator driving the AVDD pin < 10. This value is the sum of input R/F and output R/F. Guaranteed by design and characterization.
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16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
SHIFT SSEL (SAS = 0)
SAMPLE
SHIFT
SAMPLE
tMCK 1/0 SCLK CKPOL/CKPHA 0/1 tMCH 1/1 SCLK CKPOL/CKPHA 0/0 tMOH tMOV MOSI MSB MSB-1 tRF LSB tMLH tMCL 1/1 0/0 1/0 0/1
tMIS MISO MSB MSB-1
tMIH LSB
Figure 1. Enhanced SPI Master Timing
SHIFT SSEL (SAS = 0) tSSE
SAMPLE
SHIFT
SAMPLE tSSH
tSCK SCLK CKPOL/CKPHA 0/1 tSCH SCLK CKPOL/CKPHA 1/1 tSCL
tSD
tSIS MOSI MSB tSOV MISO MSB MSB-1 MSB-1
tSIH LSB tRF LSB tSLH
Figure 2. Enhanced SPI Slave Mode Timing (CKPHA = 1)
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16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
SHIFT SSEL (SAS = 0) tSSE
SAMPLE
SHIFT
SAMPLE tSSH
tSCK SCLK CKPOL/CKPHA 1/0 tSCH SCLK CKPOL/CKPHA 0/0 tSCL
tSD
tSIS MOSI MSB tSOV MISO MSB MSB-1 MSB-1
tSIH LSB tRF LSB tSLH MSB
Figure 3. Enhanced SPI Slave Mode Timing (CKPHA = 0)
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16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
I2C BUS CONTROLLER AC CHARACTERISTICS
(VDVDD = 1.8V to 3.6V, TA = -40C to +85C.) (See Figure 4.)
PARAMETER Input Low Voltage Input High Voltage Input Hysteresis (Schmitt) Output Logic-Low (Open Drain or Open Collector) Output Fall Time from VIH(MIN) to VIL(MAX) with Bus Capacitance from 10pF to 400pF (Notes 17, 18) Pulse Width of Spike Filtering That Must Be Suppressed by Input Filter Input Current Each I/O Pin with an Input Voltage Between 0.1 x VDVDD and 0.9 x VDVDD(MAX) (Note 19) I/O Capacitance SYMBOL VIL_I2C VIH_I2C VIHYS_I2C VOL_I2C VDVDD > 2V VDVDD > 2V, 3mA sink current 0 0.4 TEST CONDITIONS STANDARD MODE MIN -0.5 0.7 x VDVDD MAX 0.3 x VDVDD FAST MODE MIN -0.5 0.7 x VDVDD 0.05 x VDVDD 0 0.4 MAX 0.3 x VDVDD (Note 15) (Note 16) UNITS V V V V
MAXQ8913
t OF_I2C
250
20 + 0.1CB
250
ns
t SP_I2C
0
50
ns
I IN_I2C
-10
+10
-10
+10
A
CIO_I2C
10
10
pF
Note 15: Devices that use nonstandard supply voltages that do not conform to the intended I2C-bus system levels must relate their input levels to the VDVDD voltage to which the pullup resistors RP are connected. Note 16: Maximum VIH_I2C = VDVDD(MAX) + 0.5V. Note 17: CB = capacitance of one bus line in pF. Note 18: The maximum fall time of 300ns for the SDA and SCL bus lines as shown in the I2C Bus Controller Timing table is longer than the specified maximum tOF_I2C of 250ns for the output stages. This allows series protection resistors (Rs) to be connected between the SDA/SCL pins and the SDA/SCL bus lines as shown in the I2C Bus Controller Timing (Acting as I2C Slave) table without exceeding the maximum specified fall time. See Figure 4. Note 19: I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VDVDD is switched off.
VDVDD
VDVDD
I2C DEVICE
I2C DEVICE RP RP
RS SDA SCL
RS
RS
RS
Figure 4. Series Resistors (RS) for Protecting Against High-Voltage Spikes
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16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
I2C BUS CONTROLLER TIMING
(All values referenced to VIH_I2C(MIN) and VIL_I2C(MAX). See Figure 5.)
PARAMETER Operating Frequency Hold Time After (Repeated) START Clock Low Period Clock High Period Setup Time for Repeated START Hold Time for Data (Notes 20, 21) Setup Time for Data (Note 22) SDA/SCL Fall Time (Note 23) SDA/SCL Rise Time (Note 23) Setup Time for STOP Bus-Free Time Between STOP and START Capacitive Load for Each Bus Line Noise Margin at the Low Level for Each Connected Device (Including Hysteresis) Noise Margin at the High Level for Each Connected Device (Including Hysteresis) SYMBOL f I2C tHD:STA tLOW_I2C tHIGH_I2C t SU:STA tHD:DAT t SU:DAT tF_I2C tR_I2C t SU:STO tBUF CB VNL_I2C VNH_I2C 0.1 x VDVDD 0.2 x VDVDD 4.0 4.7 400 0.1 x VDVDD 0.2 x VDVDD STANDARD MODE MIN 0 4.0 4.7 4.0 4.7 0 250 300 1000 3.45 MAX 100 FAST MODE MIN 0 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 1.3 400 300 300 0.9 MAX 400 UNITS kHz s s s s s ns ns ns s s pF V V
Note 20: A device must internally provide a hold time of at least 300ns for the SDA signal (referenced to the VIH_I2C(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 21: The maximum tHD:DAT need only be met if the device does not stretch the low period (tLOW_I2C) of the SCL signal. Note 22: A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU:DAT 250ns must be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tR_I2C(MAX) + tSU:DAT = 1000 + 250 = 1250ns (according to the standard-mode I2C specification) before the SCL line is released. Note 23: CB = Total capacitance of one bus line in pF.
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16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
I2C BUS CONTROLLER TIMING (ACTING AS I2C MASTER)
PARAMETER System Frequency Operating Frequency Hold Time After (Repeated) START Clock Low Period Clock High Period Setup Time for Repeated START Hold Time for Data Setup Time for Data SDA/SCL Fall Time SDA/SCL Rise Time Setup Time for STOP Bus-Free Time Between STOP and START Capacitive Load for Each Bus Line Noise Margin at the Low Level for Each Connected Device (Including Hysteresis) Noise Margin at the High Level for Each Connected Device (Including Hysteresis) SYMBOL f SYS f I2C tHD:STA tLOW_I2C tHIGH_I2C t SU:STA tHD:DAT t SU:DAT tF_I2C tR_I2C t SU:STO tBUF CB VNL_I2C VNH_I2C 0.1 x VDVDD 0.2 x VDVDD tHIGH_I2C tLOW_I2C 400 0.1 x VDVDD 0.2 x VDVDD tHIGH_I2C 5 3 tLOW_I2C 0 250 300 1000 3.45 STANDARD MODE MIN 1 f SYS/8 tHIGH_I2C 5 3 tLOW_I2C 0 100 20 + 0.1CB 20 + 0.1CB tHIGH_I2C tLOW_I2C 400 300 300 0.9 MAX FAST MODE MIN 3.60 f SYS/8 MAX UNITS MHz Hz s t SYS t SYS s s ns ns ns s s pF V V
MAXQ8913
I2C BUS CONTROLLER TIMING (ACTING AS I2C SLAVE)
PARAMETER System Frequency Operating Frequency System Clock Period Hold Time After (Repeated) START Clock Low Period Clock High Period Setup Time for Repeated START Hold Time for Data Setup Time for Data SDA/SCL Fall Time SDA/SCL Rise Time Setup Time for STOP Bus-Free Time Between STOP and START Capacitive Load for Each Bus Line Noise Margin at the Low Level for Each Connected Device (Including Hysteresis) Noise Margin at the High Level for Each Connected Device (Including Hysteresis) SYMBOL f SYS f I2C t SYS tHD:STA tLOW_I2C tHIGH_I2C t SU:STA tHD:DAT t SU:DAT tF_I2C tR_I2C t SU:STO tBUF CB VNL_I2C VNH_I2C 0.1 x VDVDD 0.2 x VDVDD 3t SYS 5t SYS 400 0.1 x VDVDD 0.2 x VDVDD 1/f I2C 3t SYS 5t SYS 3t SYS 5t SYS 0 250 300 1000 3.45 3t SYS 5t SYS 3t SYS 5t SYS 0 100 20 + 0.1CB 20 + 0.1CB 3t SYS 5t SYS 400 300 300 0.9 STANDARD MODE MIN 1 f SYS/8 MAX FAST MODE MIN 3.60 f SYS/8 1/f I2C MAX UNITS MHz Hz s s s s s s ns ns ns s s pF V V
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16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
S
Sr
P
S
SDA tF_I2C tLOW SCL tHD:STA tHIGH tR_I2C tSU:DAT tSU:STA tBUF
tHD:DAT
tSU:STO
NOTE: TIMING REFERENCED TO VIH_I2C(MIN) AND VIL_I2C(MAX).
Figure 5. I2C Timing Diagram
3FF 3FE OUTPUT CODE (HEX) 3FD
FS = VREF 1 LSB = VREF/1024 ZS = 0 OUTPUT CODE (HEX)
1FF 1FE
+FS = VREF/2 -FS = -VREF/2 1 LSB = VREF/1024 ZS = 0
001 000 3FF
004 003 002 FS - 0.5 LSB 001 000 1 2 3 4 FS
201 200 -FS
-FS + 0.5 LSB
+FS - 0.5 LSB
0 INPUT VOLTAGE (LSB)
+FS
INPUT VOLTAGE (LSB)
Figure 6. Single-Ended Unipolar Transfer Function
Figure 7. Differential Bipolar Transfer Function
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16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
Block Diagram
OUTA INAAIN2 INA+ OUTB INBAIN3 INB+ OUTC INCAIN4 INC+ OUTD INDAIN5 IND+ 1.5V REFERENCE SYNCIN FAULT SHDNR SHDNL 10-BIT DAC LIN+ LINDAC2 10-BIT DAC RIN+ RINDAC1 MAXQ20 16-BIT RISC CORE
MAXQ8913
REFA
CLASS D-AMP CONTROL
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 DAC3 CURRENT SINK MUX
AVDD REF 12-BIT SAR DAC TEMP SENSOR 8-BIT DAC 8-BIT AIN6 AGND WATCHDOG TIMER POWER-ON RESET, BROWNOUT MONITOR DVDD DGND AVDD AGND RST P0.0/INT0/TCK P0.1/INT1/TDI P0.2/INT2/TMS P0.3/INT3/TDO P0.4/INT4/SSEL P0.5/INT5/SCLK P0.6/INT6/MOSI P0.7/INT7/MISO
MAXQ8913
1.8V CORE LDO REG
REG18
SINK1
DAC4 CURRENT SINK
8-BIT DAC 8-BIT JTAG PORT 0 AND INTERRUPT
SINK2
FLASH 64KB SRAM 4KB UTILITY ROM 4KB HFXIN HFXOUT CLOCK GENERATOR RC OSC, HF CRYSTAL OSC, 1MHz RING OSC
4-WIRE (SPI) INTERFACE
I2 C USART TIMER B 16 x 16 HARDWARE MULTIPLY ACCUMULATE UNIT PORT 1 AND INTERRUPT P1.0/INT8/SCL/TX P1.1/INT9/SDA/RX P1.2/INT10/TB0A P1.3/INT11/TB0B
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16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
Pin Description
PIN L4 M5 E4 B5 K1 NAME POWER PINS DVDD DGND AVDD AGND REG18 Digital Supply Voltage Digital Ground Analog Supply Voltage Analog Ground Regulator Output. This pin must be connected to ground through a 1.0F capacitor. It provides the 1.8V internal regulated output. This pin is not meant to provide power externally. ANALOG MEASUREMENT PINS G2 REFA Analog Voltage Reference. When using an external reference source, this pin must be connected to 1F and a 0.01F filter capacitors in parallel. When using an internal reference source, this pin must be connected to a 0.01F capacitor. The external reference can only be used for the ADC. Operational Amplifier A Noninverting Input. This analog input pin serves as the operational amplifier A noninverting input. Operational Amplifier A Inverting Input. This analog input pin serves as the operational amplifier A inverting input. Operational Amplifier A Output. This analog input pin serves as the operational amplifier A output. This pin is also internally connected to the ADC input mux. Operational Amplifier B Noniverting Input. This analog input pin serves as the operational amplifier B noninverting input. Operational Amplifier B Inverting Input. This analog input pin serves as the operational amplifier B inverting input. Operational Amplifier B Output. This analog input pin serves as the operational amplifier B output. This pin is also internally connected to the ADC input mux. Operational Amplifier C Noninverting Input. This analog input pin serves as the operational amplifier C noninverting input. Operational Amplifier C Inverting Input. This analog input pin serves as the operational amplifier C inverting input. Operational Amplifier C Output. This analog input pin serves as the operational amplifier C output. This pin is also internally connected to the ADC input mux. Operational Amplifier D Noninverting Input. This analog input pin serves as the operational amplifier A noninverting input. Operational Amplifier D Inverting Input. This analog input pin serves as the operational amplifier D inverting input. Operational Amplifier D Output. This analog input pin serves as the operational amplifier D output. This pin is also internally connected to the ADC input mux. ADC Input 0, 1. These two analog pins function as single-ended ADC inputs or a differential pair. DAC3 Single-Ended Output DAC4 Single-Ended Output Programmable Current Sink 1 Programmable Current Sink 2 FUNCTION
A8 B7 B9 D3 A2 B3 E2 C2 B1 F1 F3 D1 H1 H3 C6 C4 A6 A4
INA+ INAOUTA INB+ INBOUTB INC+ INCOUTC IND+ INDOUTD AIN0 AIN1 DAC3 DAC4 SINK1 SINK2
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16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
Pin Description (continued)
PIN C8 D7 E6 D9 H9 H7 NAME DAC1 DAC2 LIN+ LINRIN+ RINFUNCTION DAC1 Buffer Output. Positive terminal of the differential DAC1's output buffered signal. DAC2 Buffer Output. Positive terminal of the differential DAC2's output buffered signal. DAC2 Output. Positive DAC output voltage to drive the left Class D amplifier. DAC2 Output. Negative DAC output voltage to drive the left Class D amplifier. DAC1 Output. Positive DAC output voltage to drive the right Class D amplifier. DAC1 Output. Negative DAC output voltage to drive the right Class D amplifier. RESET PIN Digital, Active-Low, Reset Input/Output. The CPU is held in reset when this pin is low and begins executing from the reset vector when released. The pin includes a pullup current source and should be driven by an open-drain external source capable of sinking in excess of 4mA. This pin is driven low as an output when an internal reset condition occurs. CLOCK PINS M1 HFXIN High-Frequency Crystal Input. Connect an external crystal or resonator between HFXIN and HFXOUT as the high-frequency system clock. Alternatively, HFXIN is the input for an external high-frequency CMOS clock source when HFXOUT is floating. High-Frequency Crystal Output. Connect an external crystal or resonator between HFXIN and HFXOUT as the high-frequency system clock. Alternatively, float HFXOUT when an external high-frequency CMOS clock source is connected to the HFXIN pin. SYNCIN Clock. This pin acts as the input clock to the Class D amplifier's sawtooth generator. SYNCIN is a divided system clock with the divide ratio set by programmable bits. GENERAL-PURPOSE I/O, SPECIAL FUNCTION PINS P0.0 I/O with Interrupt or JTAG Test Clock. This pin defaults as an input with weak pullup after a reset P.0.0/INT0/ and functions as a general-purpose I/O with interrupt capability. Enabling the pin's special function TCK disables the general-purpose I/O on the pin and makes the pin function as the test clock input. Note that the JTAG function can be disabled using the TAP bit in the SC register. P0.1/INT1/ TDI P0.1 I/O with Interrupt or JTAG Test Data In. This pin defaults as an input with a weak pullup after a reset and functions as a general-purpose I/O with interrupt capability. Enabling the pin's special function disables the general-purpose I/O on the pin and makes the pin function as the test data input. Note that the JTAG function can be disabled using the TAP bit in the SC register. P0.2 I/O with Interrupt or JTAG Test Mode Select. This pin defaults as an input with a weak pullup after a reset and functions as a general-purpose I/O with interrupt capability. Enabling the pin's special function disables the general-purpose I/O on the pin and makes the pin function as the test mode select. Note that the JTAG function can be disabled using the TAP bit in the SC register. The TMS should be gated high when JTAG is disabled. P0.3 I/O with Interrupt or JTAG Test Data Out. This pin defaults as an input with a weak pullup after a reset and functions as a general-purpose I/O with interrupt capability. The output function of the test data is only enabled during the TAP's Shift_IR or Shift_DR states. Enabling the pin's special function disables the general-purpose I/O on the pin and makes the pin function as the test data output. Note that the JTAG function can be disabled using the TAP bit in the SC register. P0.4 I/O with Interrupt or SPI Chip Select. This port pin functions as a bidirectional I/O pin with interrupt capability or as the SPI chip select. This port pin defaults to an input with a weak pullup after a reset and functions as a general-purpose I/O. The port pad also contains a Schmitt input circuit. P0.5 I/O with Interrupt or SPI Clock. This port pin functions as a bidirectional I/O pin with interrupt capability or as the SPI clock. This port pin defaults to an input with a weak pullup after a reset and functions as a general-purpose I/O. The port pad also contains a Schmitt input circuit.
MAXQ8913
N6
RST
J2
HFXOUT
F9
SYNCIN
M9
L8
K7
P0.2/INT2/ TMS
J6
P0.3/INT3/ TDO
N8
P0.4/INT4/ SSEL P0.5/INT5/ SCLK
M7
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15
16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
Pin Description (continued)
PIN NAME P0.6/INT6/ MOSI FUNCTION P0.6 I/O with Interrupt or Master Out-Slave In. This port pin functions as a bidirectional I/O pin with interrupt capability or as the SPI master out-slave in. This port pin defaults to an input with a weak pullup after a reset and functions as a general-purpose I/O. The port pad also contains a Schmitt input circuit. P0.7 I/O with Interrupt or Master In-Slave Out. This port pin functions as a bidirectional I/O pin with interrupt capability or as the SPI master in-slave out. This port pin defaults to an input with a weak pullup after a reset and functions as a general-purpose I/O. The port pad also contains a Schmitt input circuit. P1.0 I/O with Interrupt or I2C Clock or USART Transmit. This pin defaults to an input with a weak pullup after reset and functions as a general-purpose I/O with interrupt capability. The port pad contains a Schmitt input circuit. Enabling the pin's special function disables the general-purpose I/O on the pin and enables the I2C clock or USART transmitter function. P1.1 I/O with Interrupt or I2C Data or USART Receive. This pin defaults to an input with a weak pullup after reset and functions as a general-purpose I/O with interrupt capability. The port pad contains a Schmitt input circuit. Enabling the pin's special function disables the general-purpose I/O on the pin and enables the I2C data or USART receiver function.
L6
K5
P0.7/INT7/ MISO
N4
P1.0/INT8/ SCL/TX
M3
P1.1/INT9/ SDA/RX
K3
P1.2 I/O with Interrupt or Timer B0 Pin A. This pin defaults to an input with a weak pullup after reset P1.2/INT10/ and functions as a general-purpose I/O. The port pad contains a Schmitt input circuit. Enabling the pin's special function disables the general-purpose I/O on the pin and enables the timer B pin A TB0A function. P1.3 I/O with Interrupt or Timer B0 Pin B. This pin defaults to an input with a weak pullup after reset P1.3/INT11/ and functions as a general-purpose I/O. The port pad contains a Schmitt input circuit. Enabling the TB0B pin's special function disables the general-purpose I/O on the pin and enables the timer B pin B function. MISCELLANEOUS PINS SHDNL SHDNR FAULT Shutdown for Left Motor Driver. Shutdown signal for the motor drivers. Shutdown for Right Motor Driver. Shutdown signal for the motor drivers. Fault Indicator. Thermal or short circuit fault indicator from the driver IC. NO CONNECTION PINS
L2
E8 G8 F7 D5, F5, G6, G4, H5, J4, J8, K9, N2
N.C.
No Connection. Reserved for future use. Leave these pins unconnected.
16
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16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
Detailed Description
The following is an introduction to the primary features of the microcontroller. More detailed descriptions of the device features can be found in the data sheets, errata sheets, and user's guides described later in the Additional Documentation section. The 16-bit instruction word is designed for efficient execution. Bit 15 indicates the format for the source field of the instruction. Bits 0 to 7 represent the source for the transfer. Depending on the value of the format field, this can be either an immediate value or a source register. If this field represents a register, the lower 4 bits contain the module specifier and the upper 4 bits contain the register index in that module. Bits 8 to 14 represent the destination for the transfer. This value always represents a destination register, with the lower 4 bits containing the module specifier and the upper 3 bits containing the register subindex within that module. Any time that it is necessary to directly select one of the upper 24 registers as a destination, the prefix register, PFX, is needed to supply the extra destination bits. This prefix register write is inserted automatically by the assembler and requires only one additional execution cycle.
MAXQ8913
MAXQ Core Architecture
The MAXQ core is a low-cost, high-performance, CMOS, fully static, 16-bit RISC microcontroller with flash memory. The MAXQ8913 supports 7 channels of high-performance measurement using a 10-bit successive approximation register (SAR) ADC with internal reference. These parts are structured on a highly advanced, accumulator-based, 16-bit RISC architecture. Fetch and execution operations are completed in one cycle without pipelining because the instruction contains both the op code and data. The result is a streamlined microcontroller performing at up to 1 million instructions per second (MIPS) for each MHz of the system operating frequency. The highly efficient core is supported by a 16-level hardware stack, enabling fast subroutine calling and task switching. Data can be quickly and efficiently manipulated with three internal data pointers. Multiple data pointers allow more than one function to access data memory without having to save and restore data pointers each time. The data pointers can automatically increment or decrement following an operation, eliminating the need for software intervention. As a result, application speed is greatly increased.
Memory Organization
The device incorporates several memory areas: * 4KB utility ROM * 64KB of flash memory for program storage * 4KB of SRAM for storage of temporary variables * 16-level stack memory for storage of program return addresses and general-purpose use The incorporation of flash memory allows the devices to be reprogrammed multiple times allowing modifications to user applications post production. Additionally, the flash can be used to store application information including configuration data and log files. The default memory organization is organized as a Harvard architecture, with separate address spaces for program and data memory. Pseudo-Von Neumann memory organization is supported through the utility ROM for applications that require dynamic program modification and execution from RAM. The pseudo-Von Neumann memory organization places the code, data and utility ROM memories into a single contiguous memory map.
Instruction Set
The instruction set is composed of fixed-length, 16-bit instructions that operate on registers and memory locations. The instruction set is highly orthogonal, allowing arithmetic and logical operations to use any register along with the accumulator. Special function registers control the peripherals and are subdivided into register modules. The family architecture is modular so new devices and modules can reuse code developed for existing products. The architecture is transport triggered. This means that writes or reads from certain register locations can also cause side effects to occur. These side effects form the basis for the higher level op codes defined by the assembler, such as ADDC, OR, JUMP, etc. The op codes are actually implemented as MOVE instructions between certain register locations, while the assembler handles the encoding, which need not be a concern to the programmer.
Stack Memory
A 16-bit-wide hardware stack provides storage for program return addresses and can also be used as general-purpose data storage. The stack is used automatically by the processor when the CALL, RET, and RETI instructions are executed and when an interrupt is serviced. An application can also store values in the stack explicitly by using the PUSH, POP, and POPI instructions.
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16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
On reset, the stack pointer, SP, initializes to the top of the stack (0Fh). The CALL, PUSH, and interrupt-vectoring operations increment SP, then store a value at the location pointed to by SP. The RET, RETI, POP, and POPI operations retrieve the value at SP and then decrement SP.
reduce the life-cycle cost of the embedded system. These features can be password protected to prevent unauthorized access to code memory.
Utility ROM
The utility ROM is a 4KB block of internal ROM memory that defaults to a starting address of 8000h. The utility ROM consists of subroutines that can be called from application software. These include the following: * In-system programming (bootstrap loader) using JTAG interface * In-circuit debug routines * Test routines (internal memory tests, memory loader, etc.) * User-callable routines for in-application flash programming and fast table lookup Following any reset, execution begins in the utility ROM. The ROM software determines whether the program execution should immediately jump to location 0000h, the start of user-application code, or to one of the special routines mentioned. Routines within the utility ROM are user accessible and can be called as subroutines by the application software. More information on the utility ROM contents is contained in the MAXQ Family User's Guide: MAXQ8913 Supplement. Some applications require protection against unauthorized viewing of program code memory. For these applications, access to in-system programming, inapplication programming, or in-circuit debugging functions is prohibited until a password has been supplied. The password is defined as the 16 words of physical program memory at addresses 0010h to 001Fh. A single password lock (PWL) bit is implemented in the SC register. When the PWL is set to one (power-on reset default) and the contents of the memory at addresses 0010h to 001Fh are any value other than FFh or 00h, the password is required to access the utility ROM, including in-circuit debug and in-system programming routines that allow reading or writing of internal memory. When PWL is cleared to zero, these utilities are fully accessible without password. The password is automatically set to all ones following a mass erase.
(Bootloader) In-System Programming An internal bootstrap loader allows the device to be reloaded over a simple JTAG interface. As a result, software can be upgraded in-system, eliminating the need for a costly hardware retrofit when updates are required. Remote software updates enable application updates to physically inaccessible equipment. The interface hardware can be a JTAG connection to another microcontroller or a connection to a PC serial port using a serial-to-JTAG converter such as the MAXQJTAG-001, available from Maxim. If in-system programmability is not required, a commercial gang programmer can be used for mass programming. Activating the JTAG interface and loading the test access port (TAP) with the system programming instruction invokes the bootstrap loader. Setting the SPE bit to 1 during reset through the JTAG interface executes the bootstrap-loader mode program that resides in the utility ROM. When programming is complete, the bootstrap loader can clear the SPE bit and reset the device, allowing the device to bypass the utility ROM and begin execution of the application software. The following bootstrap loader functions are supported: * Load
* Dump * CRC * Verify * Erase
In-Application Programming The in-application programming feature allows the microcontroller to modify its own flash program memory while simultaneously executing its application software. This allows on the fly software updates in mission-critical applications that cannot afford downtime. Alternatively, it allows the application to develop custom loader software that can operate under the control of the application software. The utility ROM contains user-accessible flash programming functions that erase and program flash memory. These functions are described in detail in the MAXQ Family User's Guide: MAXQ8913 Supplement.
Programming
The flash memory of the microcontroller can be programmed by two different methods: in-system programming and in-application programming. Both methods afford great flexibility in system design as well as
18
Register Set
Most functions of the device are controlled by sets of registers. These registers provide a working space for memory operations as well as configuring and addressing peripheral registers on the device. Registers are
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16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
divided into two major types: system registers and peripheral registers. The common register set, also known as the system registers, includes the ALU, accumulator registers, data pointers, interrupt vectors and control, and stack pointer. The peripheral registers define additional functionality that could be included by different products based on the MAXQ architecture. This functionality is broken up into discrete modules so that only the features required for a given product need to be included. The module and register functions are covered fully in the MAXQ Family User's Guide and the MAXQ Family User's Guide: MAXQ8913 Supplement. This information includes the locations of status and control bits and a detailed description of their function and reset values. Refer to this documentation for a complete understanding of the features and operation of the microcontroller. after timer rollover becomes effective during the following counter cycle.
MAXQ8913
Watchdog Timer
An internal watchdog timer greatly increases system reliability. The timer resets the device if software execution is disturbed. The watchdog timer is a free-running counter designed to be periodically reset by the application software. If software is operating correctly, the counter is periodically reset and never reaches its maximum count. However, if software operation is interrupted, the timer does not reset, triggering a system reset and optionally a watchdog timer interrupt. This protects the system against electrical noise or electrostatic discharge (ESD) upsets that could cause uncontrolled processor operation. The internal watchdog timer is an upgrade to older designs with external watchdog devices, reducing system cost and simultaneously increasing reliability. The watchdog timer is controlled through bits in the WDCN register. Its timeout period can be set to one of four programmable intervals ranging from 212 to 221 system clocks in its default mode, allowing flexibility to support different types of applications. The interrupt occurs 512 system clocks before the reset, allowing the system to execute an interrupt and place the system in a known, safe state before the device performs a total system reset. At 10MHz, watchdog timeout periods can be programmed from 410s to 54s, depending on the system clock mode.
Programmable Timer
The microcontroller incorporates one instance of the 16-bit programmable timer/counter B peripheral. It can be used in counter/timer/capture/compare/PWM functions, allowing precise control of internal and external events. The timer/counter supports clock input prescaling and set/reset/toggle PWM/output control functionality not found on other MAXQ timer implementations. A new register, TBC, supports PWM/output control functions. A distinguishing characteristic of timer/counter B is that its count ranges from 0000h to the value stored in the 16-bit capture/reload register (TBR) counting up. The timer/counter B timer is fully described in the MAXQ Family User's Guide: MAXQ8913 Supplement. Timer B operational modes include the following: * Autoreload * Autoreload using external pin * Capture using external pin * Up/down count using external pin * Up-count PWM/output * Up/down PWM/output * Clock output on TBxB pin * Up/down PWM mode with double-buffered output mode: * On interrupt, the user loads buffered output data, which does not begin sending until current iteration is completed. This enables a glitchless PWM because there is no output pause while interrupt is being serviced, and a race condition does not occur in setting TBC before it is used. A TBC value written
Op Amps
The MAXQ8913 contains four uncommitted op amps. It is electrically acceptable for op-amp outputs to exceed the reference voltage, but they saturate the ADC code. Gains and offsets introduced in the op-amp circuits should be carefully set to maintain the outputs of the op amps at or below the reference voltage if the ADC converted values are expected to be unsaturated. The device provides REFA as an output to aid in this endeavor. The outputs of the op amps are internally connected to ADC channels 2 to 5. Unused op amps should be connected with their "+" input terminal grounded and the output and "-" input terminals shorted together.
Differential DAC and External Class D Amplifier Output Stage Operation
The power stage of the MAXQ8913 is designed to drive a stereo Class D amplifier (DAMP). These amplifiers are
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19
16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
suitable for driving self-commutating DC motors or voice coil motors. Each external DAMP is differentially driven by a 10-bit DAC. The DAC output common mode is 1.25V, based on the bandgap reference, and each differential output can swing from GND to 2.5V (if VDVDD 3V), so the effective differential peak-to-peak voltage is 5V. The DAMP has a 6dB gain, so its ouput can swing 10V (if DAMP supply = 5V). The differential output voltage follows the simple formula: VDIFF = 2.5 x (code - 512)/512V There are four Class D amplifier control bits and one status bit. The SHDNR and SHDNL pins are the activehigh shutdown controls for the two Class D amplifiers, respectively. The SYNCIN_DIV bits control the input clock to the Class D amplifier sawtooth generator. The SYNCIN frequency must fall within 2MHz and 2.8MHz. The optimal frequency is 2.2MHz. The frequency of the high-frequency oscillator and the divide ratio need to be chosen wisely to accomodate this requirement. For example, if a 9MHz crystal is used, a divide-by-4 ratio produces a SYNCIN frequency of 2.25MHz. Table 1 shows the divide ratio applied to the high-frequency oscillator output based on the value of SYNCIN_DIV.
The DAMP FAULT bit goes high for at least 500ns following a thermal shutdown or current-limit event. It stays low in shutdown and is glitch-free during powerup. FAULT interrupts the microcontroller if enabled. Alternatively, the firmware can poll the bit periodically to detect faults of the type previously described.
DAC1 and DAC2 Buffers
While the MAXQ8913 contains power drivers for the actuator, the positive terminal of each differential DAC output pair is buffered and available as an output pin. This feature is intended primarily for test, and no significant load should be added to the DAC1 and DAC2 pins. The specifications for these pins are not yet determined, except for the no-load output voltage, which is expected to be between GND and 2.5V.
DAC3 and DAC4
DAC3 and DAC4 are single-ended DACs. Their outputs are intended for driving the positive terminal (through a resistor) of single-supply op amps to force the virtual GND to a value that allows the op amp to operate below and above the virtual ground DC value. Operated in this fashion, the DACs can also serve as offset cancellation devices as necessary.
SINK1 and SINK2
Popular optical-image stabilization implementations include the use of Hall-effect elements for position feedback. Hall-effect elements require a current to flow through two of its terminals for proper operation. The device includes two current sinks intended to drive these elements. The current sinks are programmable between 0 and 15.94mA with 62.5mA resolution through an 8-bit code. Code 0 turns them off. When operating Hall-effect elements from 3V, the maximum achievable current is given by (3V - 0.5V)/RHALL, where 0.5V is the minimum voltage value at the input of the current sink. For example, if RHALL = 250, the maximum current is 10mA. If higher currents are desirable, the user must provide a larger supply voltage to the Hall-effect element. In this case, care must be exercised so that the output nodes of the Hall-effect element do not exceed V AVDD . Exceeding V AVDD could cause the input-protection diodes of the op-amp terminals to begin conduction and waste power when the device is in sleep mode. If supplying a voltage larger than VAVDD to the Hall-effect element, a switchable supply is recommended to avoid the leakage path identified above.
Table 1. SYNCIN Divisor vs. SYNCIN_DIV Value
SYNCIN_DIV 0 (default) 1 2 3 HF DIVIDED BY SYNCIN clock off 2 3 4
To start operating the DACs and DAMPs, the following procedural steps should be followed: 1) Set both DAC inputs to code 512. 2) Enable the SYNCIN clock by setting an appropriate value for SYNCIN_DIV. 3) Wait 100s. Clear the SHDNR and SHDNL bits. 4) Wait 100s. One or both DAMPs can be shut down at any time by setting the corresponding SHDN bit. If both DAMPs are shut down, the firmware should disable the SYNCIN signal.
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16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
Additional Documentation
Designers must have four documents to fully use all the features of this device. This data sheet contains pin descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations from published specifications. The user's guides offer detailed information about device features and operation. * This MAXQ8913 data sheet, which contains electrical/timing specifications and pin descriptions. * The MAXQ8913 errata sheet for the specific device revision, available at www.maxim-ic.com/errata. * The MAXQ Family User's Guide, which contains detailed information on core features and operation, including programming. This document is available on our website at www.maxim-ic.com/MAXQUG. * The MAXQ Family User's Guide: MAXQ8913 Supplement, which contains detailed information on features specific to the MAXQ8913.
Development and Technical Support
A variety of highly versatile, affordably priced development tools for this microcontroller are available from Maxim and third-party suppliers, including: * Compilers * In-circuit emulators * Integrated development environments (IDEs) * JTAG-to-serial converters for programming and debugging. A partial list of development tool vendors can be found at www.maxim-ic.com/MAXQ_tools. For technical support, go to https://support.maximic.com/micro.
MAXQ8913
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 58 WLP PACKAGE CODE W584B2+1 DOCUMENT NO. 21-0220
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21
16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
Pin Configuration
MAXQ8913
TOP VIEW 1 2 3 4 5 6 7 8 9
+
A
INB-
SINK2
SINK1
INA+
B
OUTC
OUTB
AGND
INA-
OUTA
C
INC-
DAC4
DAC3
DAC1
D
OUTD
INB+
N.C.
DAC2
LIN-
E
INC+
AVDD
LIN+
SHDNL
F
IND+
IND-
N.C.
FAULT
SYNCIN
G
REFA
N.C.
N.C.
SHDNR
H
AIN0
AIN1
N.C. P0.3/ INT3/ TDO P0.7/ INT7/ MISO DVDD P0.6/ INT6/ MOSI DGND P1.0/ INT8/SCL/ TX
RIN-
RIN+
J
HFXOUT P1.2/ INT10/ TBOA P1.3/ INT11/ TB0B HFXIN P1.1/ INT9/SDA/ RX N.C.
N.C.
N.C. P0.2/ INT2/ TMS P0.1/ INT1/ TDI P0.5/ INT5/ SCLK P0.0/ INT0/ TCK P0.4/ INT4/ SSEL
K
REG18
N.C.
L
M
N
RST
WLP
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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